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Partitioning a Linux based hard drive means dividing it into many logical drives, each of which is considered as an independent disk. Linux supports different disk partitioning software such as cfdisk (curses based version of fdisk), parted (GNU partition editor), sfdisk (command line version of fdisk) and of course the basic one, fdisk. At times you encounter errors that force you to remove all the existing partitions. In such situations, it becomes essential that you use your recent data backup and restore the lost information. But sometimes, you find that your backup is not as productive that could offer complete data restoration results. Thus, to overcome such situations, you need to use Linux Recovery tools. While trying to execute cfdisk as root to perform tasks like formatting the partition, you get the similar error message on screen:"FATAL ERROR: Bad primary partition : Partition ends in the final partial cylinder"* cfdisk is an improved curses based version o fdi sk. This Linux partition editor is a part of util-linux package included in Linux utility programs. CauseThe above error message occurs if the existing partitions are not in correct layout. cfdisk gives this error message when it detects hard drive partitions in bad order or overlapped. Solution To fix the above issue, you should correct the present disk layout. You can perform this by removing all the existing partitions and creating new ones. To do so, use any of these methods:* Try using cfdisk -z /dev/device command* Make use of disk partitioning utilities like fdisk, gparted etc. You may fail to repartition the hard drive using cfdisk as it prompts errors until it finds issues with disk layout. Using any of the methods, described above, all the data that exists on disk gets deleted. Therefore, to restore the lost information, you should check your data backup status and restore from it. If backup cannot give the required results, scan your disk using Linux Data Recovery applications. Linux Recovery software are specifically designed tools to locate the missing information and restore it safely. In addition, you find these products with interactive interface equipped with rich graphic tools. Stellar Phoenix Linux Data Recovery is the finest Linux Recovery utility. It incorporates powerful scanning algorithms, read-only design, intuitive interface and advanced features. It supports data recovery for Ext2, Ext3 and ReiserFS file systems. It is compatible with most of the Linux distributions- Red Hat, SUSE, Caldera, Mandrake, TurboLinux, Slackware, Gentoo etc.

LILO (LInux LOader) is the standard boot loader used for Linux systems. When you start a LILO installed system, it undergoes two major stages to boot successfully: first stage (in boot sector) and second stage (in /boot/boot.b file). LILO finds all the required sector addresses in a map file called /boot/map, which is created when you install LILO. With the success of each stage while booting a LILO installed system, it displays a letter. It implies if it is displaying complete word-LILO, the boot process is successful. If the process encounters any discrepancies, it will halt displaying an error on screen. In critical situations, you might need to reformat the drive and use your recent data backup or Linux Recovery tools to restore lost data. As an instance, when you start a Linux-based system, it might the letter 'L", followed by a 2-digit error code. The error code could be 01, 07, 0C etc. CauseA Linux system displays the letter 'L' when the first-stage boot loader load s successully but it cannot continue to load second stage boot loader. The general causes for such errors to occur are bad parameters in BIOS, geometry mismatch, LILO corruption and media failure issues. However, to determine the exact cause, you should refer to the 2-digit error code following the letter 'L'. SolutionTo troubleshoot such problems, you can try performing steps like:* If LILO is corrupted, remove and reinstall it. To remove LILO, use this command:lilo -u /dev/hdaFor reinstalling LILO, run LILO command as root. * You can try specifying linear option at the top of /etc/lilo.conf file.* You should check your BIOS setting to make sure that the specified hard disk geometry matches with that of your hard drive. You can use the following command to get the hard drive geometry details:hdparm -g /dev/hda* Try putting LILO on a different partition and making it bootable by using fdsik. * Run fsck, hard drive might be corrupted. Reforat the hard drive if fsck doesn't re solve the issue. You will need to use your backup to restore lost information the hard drive or use Data Recovery Linux tools after reformatting. Designed with powerful Linux Recovery algorithms, these utilities serve as safe products to recover lost data. Stellar Phoenix Linux Data Recovery is a comprehensive tool to recover lost data. It supports Ext2, Ext3 and Reiser FS file systems. With advanced options like RAW File Recovery, Disk Imaging, File Filter etc., it is a user-friendly application. This Data Recovery Linux tool is compatible with almost all Linux distributions like SUSE, Red Hat, SlackWare, Turbo Linux, Gentoo etc.

Will Windows 8 block users from dual-booting Linux? Microsoft won't say

Some are concerned that Microsoft's coming Windows 8 secure-boot technologies and policies could result in users being unable to dual-boot Linux alongside Windows 8. Microsoft officials aren't commenting on whether the worries are unfounded or grounded.

There's a report circulating -- originating with a Red Hat employee -- that says Microsoft's new secure-boot functionality in Windows 8 could preclude users from running both Windows and Linux on their PCs.

True or false? Well-grounded or unfounded? Microsoft execs will not comment -- which is leading many to assume it's true.

Matthew Garrett, a power management and mobile Linux developer at Red Hat, blogged about the possible lock-out scenario on September 20. He explained how the Unified Extensible Firmware Interface (UEFI) technology and Microsoft's secure-boot plans -- outlined in a new blog post on the "Building Windows 8 blog this week -- potentially could thwart those who want to dual boot Linux and Windows 8 on their Windows 8 machines.

Garrett's conclusion: "It's probably not worth panicking yet. But it is worth being concerned."

Microsoft officials have said -- via a UEFI session at the company's recent Build conference, along with the aforementioned blog post -- all that they are going to say on the topic.

Here's what Microsoft has said, re: its secure boot plans for Windows 8. These tidbits are from the previously mentioned Build session on UEFI:

All firmware and software in the boot process must be signed by a trusted Certificate Authority (CA)Required for Windows 8 clientDoes not require a Trusted Platform Module (TPM)Reduces the likelihood of bootkits, rootkits and ransomwareAnother slide from the same talk:

Garrett's interpretation of Microsoft's shared information on the topic:

"Microsoft requires that machines conforming to the Windows 8 logo program and running a client version of Windows 8 ship with secure boot enabled. The two alternatives here are for Windows to be signed with a Microsoft key and for the public part of that key to be included with all systems, or alternatively for each OEM to include their own key and sign the pre-installed versions of Windows. The second approach would make it impossible to run boxed copies of Windows on Windows logo hardware, and also impossible to install new versions of Windows unless your OEM provided a new signed copy. The former seems more likely.

"A system that ships with only OEM and Microsoft keys will not boot a generic copy of Linux."

I can't resist a rant here: The Windows team's decision not to comment on this report is an example of the new communication strategy that Microsoft seems to be instituting with Windows 8: Clarification on any Windows 8 topic -- not only features and policies that are still unannounced, but also those that already have been disclosed publicly -- apparently will not be provided by anyone from Microsoft in an official capacity. The result: An increasing amount of misinformation about Windows 8 is circulating, and Microsoft is doing little or nothing to correct it.

I understand Microsoft's increased desire for secrecy around its Windows plans, somethingcompany officials began pushing post-Vista. (I haven't always agreed with the goal, especially when it results in FUD for customers attempting to make rational buying decisions or OEM/ISV partners attempting to build products that work with Windows.) But allowing wrong information to go unchecked in the name of wanting to control the message and the way it is delivered seems like bad business to me.

Back on topic: Does anyone out there have any more to share (in an official capacity or not) about whether you think the new Windows 8 secure boot technologies and policies will block users from dual-booting Linux? Ars Technica's take: "Ultimately, the Windows 8 changes aren't likely to wipe out Linux dual-boot scenarios, but they could restrict the types of hardware that will allow them." Other opinions?

Read more: /battery-technology/what-windows-8-must-bring-the-big-windows-8-tablet-challenge/

Ever wondered how does a website operate? By simply typing a name, how does a user land on a website? This phenomenon is accomplished by taking a Web Hosting service. It is a service by which users get to publish their websites on the internet. The companies that offer this service basically allocate certain space on their servers to website owners. Still not sure what exactly this service is? Let us go ahead and find out what this service is and how to go about choosing a reliable hosting service provider.

Web Hosting is a service that allows a user to publish his website on the web. Web Hosting is a service that allows a user to publish his website on the web. Web hosts basically provide some space on web servers to users. These servers can be defined as powerful computers that are constantly connected to internet. Now the question arises how to go about selecting a web host? It is one of the most crucial concerns a user has. Choosing a web host can be very trickier at times, as there are number of companies that provide hosting services. The user is first advised to find out his hosting requirements. He should always do some research before zeroing on one service provider. Things that a user must look for in a reliable web host are:

Reputation and Reliability Uptime Guarantee Speed Technical Support Customer Service

Windows and Linux are two operating systems that are used hosting a website. As the names suggest Windows Hosting is achieved using a windows operating system, while Linux Hosting is attained via a Linux operating system. Both these hosting plans come with different set of advantages that make them different from one another. As there are several hosting companies in operation, most of them offer Linux as well as Windows Hosting plans. Windows is mostly used for websites that use various windows applications. It is comparatively costlier than Linux Hosting as it has certain licensing costs attached with it. Windows is the most extensively used operating system and is the preferred choice all starters. Linux operating system, which is an open source platform, is known to be much more user-friendly and secure. This operating system can also be upgraded very easily.

Java Hosting is also among the most popular and powerful hosting option for users. It is considered an ideal alternative for users who are seeking to launch a JSP-coded website and among web designers.

Principle DMA is an essential feature of all modern computers, as it allows devices to transfer data without subjecting the CPU to a heavy overhead. Otherwise, the CPU would have to copy each piece of data from the source to the destination, making itself unavailable for other tasks. This situation is aggravated because access to I/O devices over a peripheral bus is generally slower than normal system RAM. With DMA, the CPU gets freed from this overhead and can do useful tasks during data transfer (though the CPU bus would be partly blocked by DMA). In the same way, a DMA engine in an embedded processor allows its processing element to issue a data transfer and carries on its own task while the data transfer is being performed. A DMA transfer copies a block of memory from one device to another. While the CPU initiates the transfer by issuing a DMA command, it does not execute it. For so-called "third party" DMA, as is normally used with the ISA bus, the transfer is perform ed by a DMA controller which is typically part of the motherboard chipset. More advanced bus designs such as PCI typically use bus mastering DMA, where the device takes control of the bus and performs the transfer itself. In an embedded processor or multiprocessor system-on-chip, it is a DMA engine connected to the on-chip bus that actually administers the transfer of the data, in coordination with the flow control mechanisms of the on-chip bus. A typical usage of DMA is copying a block of memory from system RAM to or from a buffer on the device. Such an operation usually does not stall the processor, which as a result can be scheduled to perform other tasks unless those tasks include a read from or write to memory. DMA is essential to high performance embedded systems. It is also essential in providing so-called zero-copy implementations of peripheral device drivers as well as functionalities such as network packet routing, audio playback and streaming video. Multicore embe dded processors (in the form of multiprocessor system-on-chip) often use one or more DMA engines in combination with scratchpad memories for both increased efficiency and lower power consumption. In computer clusters for high-performance computing, DMA among multiple computing nodes is often used under the name of remote DMA. Cache coherency problem DMA can lead to cache coherency problems. Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external memory version of X. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X. Similarly, if the cached copy of X is not invalidated when a device writes a new value to the memory, then the CPU will operate on a stale value of X. This issue can be addressed in one of two ways in system design: Cache-coherent systems implement a method in hardware whereby external writes are signaled to the cache controller which then performs a cache invalidation for DMA writes or cache flush for DMA reads. Non-coherent systems leave this to software, where the OS must then ensure that the cache lines are flushed before an outgoing DMA transfer is started and invalidated before a memory range affected by an incoming DMA transfer is accessed. The OS must make sure that the memory range is not accessed by any running threads in the meantime. The latter approach introduces some overhead to the DMA operation, as most hardware requires a loop to invalidate each cache line individually. Hybrids also exist, where the secondary L2 cache is coherent while the L1 cache (typically on-CPU) is managed by software. DMA engine In addition to hardware interaction, DMA can also be used to offload expensive memory operations, such as large copies or scatter-gather operations, from the CPU to a dedicated DMA engine. Examples ISA For example, a PC's ISA DMA[Direct memory access] controller is based on the Intel 8237 Multimode DMA controller, that is a software-hardware combination which either consists of or emulates this part. In the original IBM PC, there was only one DMA controller capable of providing four DMA channels (numbered 0-3). These DMA channels performed 8-bit transfers and could only address the first megabyte of RAM. With the IBM PC/AT, a second 8237 DMA controller, was added (channels 5-7; channel 4 is unusable), and the page register was rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller performed 16-bit transfers. Due to their lagging performance (2.5 Mbit/s), these devices have been largely obsolete since the advent of the 80386 processor and its capacity for 32-bit transfers. They are still supported to the extent they are required to support built-in legacy PC hardware on modern machines. Each DMA channel has a 16-bit address register and a 16-bit count register associated with it. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to begin the transfer. When the transfer is complete, the device interrupts the CPU. Scatter-gather DMA allows the transfer of data to and from multiple memory areas in a single DMA transaction. It is equivalent to the chaining together of multiple simple DMA requests. The motivation is to off-load multiple input/output interrupt and data copy tasks from the CPU. DRQ stands for DMA request; DACK for DMA acknowledge. These symbols, seen on hardware schematics of computer systems with DMA functionality, represent electronic signaling lines between the CPU and DMA controller. Each DMA channel has one Request and one Acknowledge line. A prop erly configured device that uses DMA must be jumpered (or software-configured) to use both lines of the assigned DMA channel. Standard ISA DMA assignments: 0 DRAM Refresh (obsolete), 1 User hardware, 2 Floppy disk controller, 3 Hard disk (obsoleted by PIO modes, and replaced by UDMA modes), 4 Cascade from XT DMA controller, 5 Hard Disk (PS/2 only), user hardware for all others, 6 User hardware, 7 User hardware. PCI As mentioned above, a PCI architecture has no central DMA controller, unlike ISA. Instead, any PCI component can request control of the bus ("become the bus master") and request to read and write from the system memory. More precisely, a PCI component requests bus ownership from the PCI bus controller (usually the southbridge in a modern PC design), which will arbitrate if several devices request bus ownership simultaneously, since there can only be one bus master at one time. When the component is granted ownership, it will issue normal read and write commands on the PCI bus, which will be claimed by the bus controller and forwarded to the memory controller using a scheme which is specific to every chipset. As an example, on a modern AMD Socket AM2-based PC, the southbridge will forward the transactions to the northbridge (which is integrated on the CPU die) using HyperTransport, which will in turn convert them to DDR2 operations and send them out on the DDR2 memory bus. As can be seen, there are quite a number of steps involved in a PCI DMA transfer; however, that poses little problem, since the PCI device or PCI bus itself are an order of magnitude slower than rest of components (see list of device bandwidths). A modern x86 CPU may use more than 4 GB of memory, utilizing PAE, a 36-bit addressing mode. In such a case, a device using DMA with a 32-bit address bus is unable to address memory above the 4 GB line. The new Double Address Cycle (DAC) mechanism, if implemented on both the PCI bus and the device itself, enables 64-bit DMA addressing. Otherwise, the operating system would need to work around the problem by either using costly double buffers (Windows nomenclature) also known as bounce buffers (Linux), or it could use an IOMMU to provide address translation services if one is present. PCI-Express PCI Express uses DMA. The DMA engine appears as another function on the upstream post with a TYPE 0 configuration header. IO Accelerator in Xeon As an example of DMA engine incorporated in a general-purpose CPU, newer Intel Xeon chipsets include a DMA engine technology called I/O Acceleration Technology (I/OAT), meant to improve network performance on high-throughput network interfaces, in particular gigabit Ethernet and faster. However, various benchmarks with this approach by Intel's Linux kernel developer Andrew Grover indicate no more than 10% improvement in CPU utilization with receiving workloads, and no improvement when transmitting data. AHB In systems-on-a-chip and embedded systems, typical sys tem bus infrastructure is a complex on-chip bus such as AMBA High-performance Bus. AMBA defines two kinds of AHB components: master and slave. A slave interface is similar to programmed I/O through which the software (running on embedded CPU, e.g. ARM) can write/read I/O registers or (less commonly) local memory blocks inside the device. A master interface can be used by the device to perform DMA transactions to/from system memory without heavily loading the CPU. Therefore high bandwidth devices such as network controllers that need to transfer huge amounts of data to/from system memory will have two interface adapters to the AHB bus: a master and a slave interface. This is because on-chip buses like AHB do not support tri-stating the bus or alternating the direction of any line on the bus. Like PCI, no central DMA controller is required since the DMA is bus-mastering, but an arbiter is required in case of multiple masters present on the system. Internally, a multichannel DM A engine is usually present in the device to perform multiple concurrent scatter-gather operations as programmed by the software. Cell As an example usage of DMA in a multiprocessor-system-on-chip, IBM/Sony/Toshiba's Cell processor incorporates a DMA engine for each of its 9 processing elements including one power-processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this CPU (in contrast to cache-coherent CMP architectures such as Intel's coming general-purpose GPU, Larrabee). DMA in Cell is fully cache coherent (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the standard sense). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to a recent experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200GB per second. See also Remote Direct Memory Access Blitter AT Attachment References ^ Intel publication 03040, Aug 1989 ^ "Physical Address Extension - PAE Memory and Windows". Microsoft Windows Hardware Development Central. 2005. /whdc/system/platform/server/PAE/PAEdrv.mspx#E2D. Retrieved 2008-04-07. ^ Corbet, Jonathan (2005-12-06). "Memory copies in hardware". LWN.net (December 8, 2005). /Articles/162966/. Retrieved 2006-11-12. ^ Grover, Andrew (2006-06-01). "I/OAT on LinuxNet wiki". Overview of I/OAT on Linux, with links to several benchmarks. /index.php/I/OAT. Retrieved 2006-12-12. ^ Kistler, Michael (2006-05). "Cell Multiprocessor Communication Network". Extensive benchmarks of DMA performance in Cell Broadband Engine. /citation.cfm?id=1158825.1159067. DMA Fundamentals on Various PC Platforms, from A. F. Harvey and Data Acquisition Division Staff NATIONAL INSTRUMENTS mmap() and DMA, from Linux Device Drivers, 2nd Edition, Alessandro Rubini & Jonathan Corbet Memory Mapping and DMA, from Linux Device Drivers, 3rd Edition, Jonathan Corbet, Alessandro Rubini, Greg Kroah-Hartman DMA and Interrupt Handling DMA Modes & Bus Mastering v d e Computer bus & interconnection standards (wired) Main articles Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Electrical bus List of bus bandwidths Computer bus standards (desktop) S-100 bus MBus SMBus Q-Bus ISA Zorro II Zorro III CAM AC FASTBUS LPC HP Precision Bus EISA VME VXI NuBus TURBOchannel MCA SBus VLB PCI PXI HP GSC bus CoreConnect InfiniBand UPA PCI-X AGP PCI Express Intel QuickPath Interconnect HyperTransport more... Computer bus standards (portable) PC Card ExpressCard Storage bus standards ST-506 ESDI SMD Parallel ATA DMA SSA HIPPI USB MSC FireWire (1394) Serial ATA eSATA SCSI Parallel SCSI Serial Attached SCSI Fibre Channel iSCSI Peripheral bus standards Multidrop bus Apple Desktop Bus HIL MIDI Multibus RS-232 (serial port) DMX512-A EIA/RS-422 IEEE-1284 (parallel port) UNI/O 1-Wire IC SPI EIA/RS-485 Parallel SCSI USB FireWire (1394) Fibre Channel Camera Link External PCI Express x16 Light Peak Vehicle buses LIN J1708 J1587 FMS J1939 CAN VAN FlexRay MOST Note: interfaces are listed in speed ascending order (roughly), the interface at the end of each section should be the fastest Categories: Computer memory | Motherboard